Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/Silicon Labs/Series1/EFM32GG11B/EFM32GG11B420F2048GQ64/ETH/RXBDCTRL#0x0
RX BD control register
RX Descriptor Timestamp Insertion mode, 00: TS insertion disable, 01: TS inserted for PTP Event Frames only, 10: TS inserted for All PTP Frames only, 11: TS insertion for All Frames
https://github.com/cmsis-svd/cmsis-svd-data